1. Field of the Invention
The present invention relates to a semiconductor device with Thin-Film Transistors (TFTs) and a method of fabricating the device. The semiconductor device according to the invention is applicable to circuit elements of Liquid-Crystal Display (LCD) devices, such as switching elements for the pixels, elements for the driver circuit, and so on. Here, it is preferred for the TFTs that the active layer is formed by a polycrystalline silicon (i.e., polysilicon) thin film.
2. Description of the Related Art
Generally, the LCD device comprises a substrate on which TFTs are arranged in a matrix array (which is termed the “TFT substrate” below), another substrate opposed to the TFT substrate at a predetermined gap (which is termed the “opposite substrate” below), and a liquid crystal layer located between the TFT substrate and the opposite substrate. With the fabrication processes of the TFT substrate, to ensure the fabrication yield and the TFT characteristics stability, it is important to correctly control the alignment between the patterns in each of the processes.
A conventional, popular method of fabricating the TFT substrate is as follows:
Specifically, first, an insulating backing film made of silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or the like is formed on a glass plate and then, an amorphous silicon film is formed on the backing film by Chemical Vapor Deposition (CVD) or the like. “Amorphous silicon” may be simplified as “a-Si” below. Thereafter, a first photosensitive resist film is formed on the a-Si film, and the a-Si film thus formed is subjected to a selective exposure process and a development process, thereby forming a first mask with a pattern for first alignment marks. Using the first mask thus formed, the a-Si film is selectively etched to form first alignment marks. After that, the first mask is removed.
Next, the a-Si film (wherein the first alignment marks have been formed) is crystallized by the solid-phase growth, the excimer laser annealing, or the like, resulting in a polycrystalline silicon film (which may be simply termed a polysilicon film below). Then, a second photosensitive resist film is formed on the polysilicon film and is subjected to a selective exposure process and a development process, resulting in a second mask with a pattern for semiconductor islands and second alignment marks. In the selective exposure process of the second photosensitive resist film, alignment is carried out using the above-described first alignment marks.
Next, using the second mask thus formed, the polysilicon film is selectively etched. Thus, the polysilicon film is patterned to form semiconductor islands (i.e., polysilicon islands). At the same time, second alignment marks are formed by the same polysilicon film. Thereafter, the second mask is removed.
Subsequently, a third photosensitive resist film is formed and is subjected to selective exposure and development processes, thereby forming a third mask with a pattern for impurity implantation. Then, using the third mask thus formed, impurity or dopant ions are selectively implanted into source/drain formation regions (which are regions to be formed as source/drain regions later and which may be termed S/D formation regions below) of the island-shaped polysilicon film (i.e., the polysilicon islands). Thus, pairs of source/drain regions (which may be termed S/D regions below) are formed in the respective polysilicon islands. After the third mask is removed, the implanted impurity ions into the polysilicon islands are activated by an excimer laser annealing process, a thermal annealing process, or the like.
Thereafter, subsequent process steps for gate insulating film formation, gate electrode/line formation, interlayer insulating film formation, contact hole formation, and source/drain line formation are carried out successively, resulting in the TFT substrate.
As explained above, with the conventional fabrication method of a TFT substrate, to form the first alignment marks only, it is necessary to conduct five process steps of formation, exposure and development of the first photosensitive resist mask, etching of the a-Si film, and removal of the first photosensitive resist mask. Therefore, there is a problem that the total number of the necessary process steps increases and the fabrication cost becomes high. So, to reduce the total number of the process steps, various measures have been developed and disclosed, an example of which is disclosed in the Japanese Non-Examined Patent Publication No. 2003-332349 published on Nov. 21, 2003. The measure disclosed in the Publication No. 2003-332349 is as follows.
Specifically, in the step of forming the a-Si film on the insulating backing film formed on the glass plate, a region where the a-Si film is not placed (i.e., an a-Si film nonexistence region) is formed on the periphery of the glass plate and at the same time, a region where the a-Si film is placed (i.e., an a-Si film formation region) is formed on the inside of the a-Si film nonexistence region on the glass plate. The a-Si film nonexistence region is formed by concealing or covering the periphery of the glass plate in the step of forming the a-Si film. Then, a photosensitive resist film is formed on both the a-Si film nonexistence region and the a-Si film formation region and then, the photosensitive resist film thus formed is selectively exposed and developed, thereby forming a mask having a pattern for impurity implantation and a pattern for alignment mark formation. The pattern for impurity implantation is placed on the a-Si film formation region, and the pattern for alignment mark formation is placed on the a-Si film nonexistence region.
Subsequently, a predetermined impurity is selectively implanted into the a-Si film using the above-described mask, and then, the insulating backing film is selectively etched using the same mask. As a result, S/D formation regions are formed in the a-Si film formation region of the a-Si film and at the same time, alignment marks are formed by the insulating backing film in the a-Si film nonexistence region. After this etching process is completed, the mask is removed.
With the method disclosed in the Publication No. 2003-332349, the above-described five process steps for forming the first alignment marks in the above-described conventional method of fabricating a TFT substrate are omitted in the above-described way. Thus, the fabrication cost increase is suppressed.
Moreover, to omit the activation process for the implanted impurity into the a-Si film to thereby shorten the fabrication process sequence, the following method was developed. This method is disclosed in the Japanese patent No. 3211340 published on Jul. 19, 2001.
Specifically, an a-Si film is deposited on an insulating plate and then, a predetermined impurity or dopant is selectively implanted into S/D formation regions of the a-Si film, thereby forming impurity-doped regions in the a-Si film. Thereafter, an excimer laser beam is directly irradiated to the impurity-doped regions, thereby turning the a-Si film into a polysilicon film (i.e., crystallization of the a-Si film) and activating the impurity existing in the impurity-doped regions simultaneously. This method is termed the excimer laser annealing method. With this method, both the crystallization of the a-Si film and the activation of the doped impurity can be carried out simultaneously and therefore, the fabrication process sequence is shortened. Consequently, fabrication cost increase is prevented.
As clearly seen from the method disclosed in the Publication No. 2003-332349, to shorten the fabrication process sequence (i.e., to reduce the total number of the necessary process steps), it is effective to form the pattern for impurity implantation and the pattern for alignment mark formation through a single set of exposure and development processes, or to simultaneously conducting the crystallization of the a-Si film and the activation of the impurity implanted into the a-Si film. However, if the pattern for impurity implantation and the pattern for alignment mark formation are formed through a single set of exposure and development processes using the method disclosed in the Publication No. 2003-332349, the alignment marks are located only on the periphery of the glass plate. Thus, a disadvantage that alignment accuracy deteriorates in the middle area of the glass plate arises.
In addition, the region for forming the alignment marks needs to be provided on the periphery of the glass plate and thus, the region for forming TFTs is narrowed. As a result, another disadvantage that the fabrication cost increases arises.
Moreover, if, similar to the method disclosed in the Japanese patent No. 3211340, a desired impurity is selectively implanted into the S/D formation regions of the a-Si film and thereafter, the crystallization of the a-Si film and the activation of the impurity ions are carried out simultaneously by excimer laser irradiation, heavy-metal impurity (which is unavoidably implanted into the surface of the a-Si film along with the desired impurity) is likely to diffuse toward the inside of the a-Si film during the excimer laser irradiation. If so, a disadvantage that the heavy-metal impurity thus diffused degrade the characteristics and reliability of the TFTs to be formed using the said a-Si film will occur.